1. Field of the Invention
The present invention relates to ROM bit cells and their method of manufacture.
2. Description of the Prior Art
ROM cells are used to store values permanently, such that on power down the value stored is not lost. ROM cells traditionally have stored a single bit value. High density ROM bit cell arrays composed of columns of bit cells have been achieved by implementing arrangements in which adjacent bit cells in the same column share a source/drain connection to an adjacent bit line or virtual ground line.
In U.S. Pat. No. 5,917,224 a compact ROM matrix is disclosed in which two adjacent columns of bit cells share a virtual ground line. FIG. 9 schematically illustrates the arrangement disclosed. A ROM bit cell array 100 is composed of transistors 112 arranged in columns, of which only three (114, 116 and 118) are shown. A high density of cells is achieved in the vertical direction by virtue of adjacent bit cells in each column sharing source or drain (generically referred to herein as “drain”) connections. These drain connections connect each transistor in each column to either a virtual ground line shared with an adjacent column of transistors or to a bit line uniquely associated with that particular column. For example the two transistors 112a and 112b illustrated in column 118 share a common drain connection to bit line BL2. Transistor 112a shares a drain connection with the transistor above it to virtual ground line 120, whilst transistor 112b shares a drain connection with the transistor below it to bit line BL2. Each transistor encodes a logical “0” or “1” by both its drain connections connecting to the same line (bit or virtual ground) or by one drain connection connecting to each kind of line. Thus when a particular bit line is charged (e.g. BL2) and a particular word line enabled (e.g. WL1), then the transistor located at the intersection of those lines (in this example transistor 112a) will manifest the logical “0” encoded by its drain connections by discharging bit line BL2 onto virtual ground line 120. Conversely if word line WL2 were enabled instead (in order to read transistor 112b), no significant discharge of the bit line would occur (both drains of transistor 112b connect to the same line), indicating a logical “1” encoded by its drain connections (it will be understood that the encoding of “1” and “0” described above is merely a convention choice and could be trivially inverted). Columns 116 and 118 share virtual ground line 120, and have their own bit lines BL1 and BL2, respectively. Similarly column 114 shares virtual ground line 122 with the column of transistors to its left (not illustrated) and has its own dedicated bit line BL0. The transistors 112 are switched in rows by word lines WL0, WL1, WL2 and WL3. For clarity the word lines are not fully illustrated.
The design of bit cells in systems such as that described above has concentrated on how to decrease the area of the cells. However, the area occupied by an array of these cells could also be improved by allowing them to store multiple bit values and thereby reducing the number required.
U.S. Pat. No. 6,636,434 discloses a ROM bit cell that has been designed to store multiple bit values. It is similar to the device of FIG. 9 but has multiple bit lines and corresponding complementary bit lines and can store a multiple bit value in a single cell by connecting to the appropriate lines. The stored values are read by sensing the difference in voltage levels between a bit line and its complementary bit line using sense amplifiers. Thus, for every additional bit that the cell can store, a bit line and its complementary bit line and an additional sense amplifier circuit are required, this is costly in area.
It would be desirable to provide a multiple bit ROM cell, without increasing the area of the cell or the cost of the output devices required unduly.